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w29ee011 128k 8 cmos flash memory publication release date: july 1999 - 1 - revision a12 general description the w29ee011 is a 1 - megabit, 5 - volt only cmos flash memory organized as 128k 8 bits. the device can be programmed and erased in - system with a standard 5v power supply. a 12 - volt v pp is not required. the unique cell architecture of the w29ee011 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5 - volt flash memory products). the device can also be programmed and erased using standard eprom programmers. features single 5 - volt program and erase operations fast page - write operations - 128 bytes per page - page program cycle: 10 ms (max.) - effective byte - program cycle time: 39 m s - optional software - protected d ata write fast chip - erase operation: 50 ms read access time: 90/150 ns page program/erase cycles: 1k/10k ten - year data reten tion software and hardware data protection low power consumption - active current: 25 ma (typ.) - standby current: 20 m a (typ.) automatic program timing with internal v pp generation end of program detection - toggle bit - data polling latched address and data ttl compatible i/o jedec standard byte - wide pinouts available packages: 32 - pin 600 mil dip, tsop, and plcc
w29ee011 - 2 - pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq0 dq1 dq2 gnd a7 a6 a5 a4 a3 a2 a1 a0 nc a16 a15 a12 v we a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 dd nc 32-pin dip 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 g n d d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 oe a10 ce dq7 a 1 2 a 1 6 n c v d d / w e a 1 5 32-pin plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 dq0 dq1 dq2 gnd oe a10 ce dq7 dq6 dq5 dq4 dq3 32-pin tsop a15 a12 a7 a6 a5 a4 v we a14 a13 a8 dd a11 a9 nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 nc n c block diagram control output buffer decoder core array ce oe we a0 . . a16 . . dq0 dq7 v dd v ss pin description symbol pin name a0 - a16 address input s dq0 - dq7 data inputs/outputs ce chip enable oe output enable we write enable v dd power supply gnd ground nc no connection
w29ee011 publication release date: july 1999 - 3 - revi sion a12 functional descripti on read mode the read operation of the w29e e011 is controlled by ce and oe , both of which have to be low for the host to obtain data from the outputs. ce is used for device selection. when ce is high, the chip is de - selected an d only standby power will be consumed. oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce or oe is high. refer to the timing w aveforms for further details. page write mode the w29ee011 is programmed on a page basis. every page contains 128 bytes of data. if a byte of data within a page is to be changed, data for the entire page must be loaded into the device. any byte that is not loaded will be erased to "ffh" during programming of the page. the write operation is initiated by forcing ce and we low and oe high. the write procedure consists of two steps. step 1 is the byte - load cycle, in which the host writes to the page buffer of the device. step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non - volatile storage. during the byte - load cycle, the addresses are latched by the falling edge of either ce or we , whichever occurs last. the data are latched by the rising edge of either ce or we , whichever occurs first. if the host loa ds a second byte into the page buffer within a byte - load cycle time (t blc ) of 200 m s, after the initial byte - load cycle, the w29ee011 will stay in the page load cycle. additional bytes can then be loaded consecutively. the page load cycle will be terminat ed and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 m s (t blco ) from the last byte - load cycle, i.e., there is no subsequent we high - to - low transition after the last rising edge o f we . a 7 to a 16 specify the page address. all bytes that are loaded into the page buffer must have the same page address. a 0 to a 6 specify the byte address within the page. the bytes may be loaded in any order; sequential loading is not required. in the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. before the completion of the internal programming cycle, the host is free to perform other tasks such as f etching data from other locations in the system to prepare to write the next page. software - protected data write the device provides a jedec - approved optional software - protected data write. once this scheme is enabled, any write operation requires a series of three - byte program commands (with specific data to a specific address) to be performed before the data load operation. the three - byte load command sequence begins the page load cycle, without which the write operation will not be activated. this write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power - up and power - down. the w29ee011 is shipped with the software data protection enabled. to enable the software data protection scheme, perform the three - byte command cycle at the beginning of a page load cycle. the device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three - byte program command cycle. once enabled, the softwa re data protection will remain enabled unless the disable commands are issued. a power transition will not reset the software data protection feature. to reset the device to unprotected mode, a six - byte command sequence is required. see table 3 for specifi c codes and figure 10 for the timing diagram.
w29ee011 - 4 - hardware data protection the integrity of the data stored in the w29ee011 is also hardware protected in the following ways: (1) noise/glitch protection: a we pulse of less than 15 ns in durat ion will not initiate a write cycle. (2) v dd power up/down detection: the programming operation is inhibited when v dd is less than 3.8v. (3) write inhibit mode: forcing oe low, ce high, or we high wil l inhibit the write operation. this prevents inadvertent writes during power - up or power - down periods. data polling (dq 7 ) - write status detection the w29ee011 includes a data polling feature to indicate the end of a programming cycle. when the w29ee011 is in the internal programming cycle, any attempt to read dq 7 of the last byte loaded during the page/byte - load cycle will receive the complement of the true data. once the programming cycle is completed. dq 7 will show the true data. toggle bit (dq 6 ) - writ e status detection in addition to data polling, the w29ee011 provides another method for determining the end of a program cycle. during the internal programming cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's. when the prog ramming cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. 5 - volt - only software chip erase the chip - erase mode can be initiated by a six - byte command sequence. after the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 ms. the host system is not required to provide any control or timing during this operation. product identification the product id operation outputs th e manufacturer code and device code. programming equipment automatically matches the device with its proper erase and programming algorithms. the manufacturer and device codes can be accessed by software or hardware operation. in the software access mode, a six - byte command sequence can be used to access the product id. a read from address 0000h outputs the manufacturer code (dah). a read from address 0001h outputs the device code (c1h). the product id operation can be terminated by a three - byte command seq uence. in the hardware access mode, access to the product id is activated by forcing ce and oe low, we high, and raising a9 to 12 volts.
w29ee011 publication release date: july 1999 - 5 - revision a12 table of operating m odes operating mode selection operating ran ge = 0 to 70 c (ambient temperature), v dd = 5v 10 % , v ss = 0v, v hh = 12v mode pins ce oe we address dq. read v il v il v ih a in dout write v il v ih v il a in din standby v ih x x x high z write inhibit x v il x x high z/d out x x v ih x high z/d out output disable x v ih x x high z 5 - volt software chip erase v il v ih v il a in d in product id v il v il v ih a0 = v il ; a1 - a16 = v il ; a9 = v hh manufacturer code da (hex) v il v il v ih a0 = v ih ; a1 - a16 = v il ; a9 = v hh device code c1 (hex)
w29ee011 - 6 - command codes for software data protection byte sequence to enable protection to disable protectio n address data address data 0 write 5555h aah 5555h aah 1 write 2aaah 55h 2aaah 55h 2 write 5555h a0h 5555h 80h 3 writ e - - 5555h aah 4 write - - 2aaah 55h 5 write - - 5555h 20h sofware data protection acquisition flow software data protection enable flow load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 software data protection disable flow pause 10 ms exit sequentially load up to 128 bytes of page data pause 10 ms exit (optional page load operation) notes for software program code: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w29ee011 publication release date: july 1999 - 7 - revision a12 command codes for software chip erase byte sequence address data 0 write 5555h aah 1 write 2aaah 55h 2 write 5555h 80h 3 write 5555h aah 4 write 2aaah 55h 5 write 5555h 10h sofware chip erase acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 10 to address 5555 pause 50 ms exit notes for software chip erase: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w29ee011 - 8 - command codes for product identification byte sequence software product identification entry software product identification exit address data address data 0 write 5555h aah 5555h aah 1 write 2 aaah 55h 2aaah 55h 2 write 5555h 80h 5555h f0h 3 write 5555h aah - - 4 write 2aaah 55h - - 5 write 5555h 60h - - pause 10 m s pause 10 m s software product identification acquisition flow product identification entry(1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 60 to address 5555 pause 10 s product identification mode(2, 3) read address = 0 data = da read address = 1 data = c1 product identification exit(1) load data aa to address 5555 load data 55 to address 2aaa load data fo to address 5555 pause 10 m m s normal mode (4) m notes for software product identification: (1) data format: dq7 - dq0 (hex); address format: a14 - a0 (hex). (2) a1 - a16 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification mode if power down. (4) the device returns to standard op eration mode.
w29ee011 publication release date: july 1999 - 9 - revision a12 dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential - 0.5 to +7.0 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential ex cept oe - 0.5 to v dd +1.0 v transient voltage (< 20 ns ) on any pin to ground potential - 1.0 to v dd +1.0 v voltage on oe pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed under ab solute maximum ratings may adversely affect the life and reliability of the device. operating characteristics (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. power supply current i cc ce = oe = v il , we = v ih , all i/os open address inputs = v il /v ih , at f = 5 mhz - - 50 ma standby v dd current (ttl input) i sb 1 ce = v ih , all i/os open other inputs = v il /v ih - 2 3 ma standby v dd current (cmos input) i sb 2 ce = v dd - 0.3v, all i/os open other inputs = v dd - 0.3v/gnd - 20 100 m a input leakage current i li v in = gnd to v dd - - 1 m a output leakage current i lo v in = gnd to v dd - - 10 m a input low voltage v il - - 0 .3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v power - up timing parameter symbol typical unit power - up to read operation t pu .read 100 m s power - up to w rite operation t pu .write 5 ms
w29ee011 - 10 - capacitance (v dd = 5.0v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf ac characteristics ac test conditions (v dd = 5v 10 % ) parameter conditions input pulse levels 0v to 3v input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf for 70 ns and 100 pf for others. ac test load and waveforms +5v 1.8k ohm d out 1.3k ohm 100 pf for 90/120/150 ns 30 pf for 70 ns (including jig and scope) input test point 0v 1.5v 3v test point 1.5v output
w29ee011 publication release date: july 1999 - 11 - revision a12 read cycle timing par ameters (v cc = 5.0v 10 % , v cc = 5.0 5 % for 70 ns, v ss = 0v, t a = 0 to 70 c) parameter sym. w29ee011 - 90 w29ee011 - 15 unit min. max. min. max. read cycle time t rc 90 - 150 - ns chip enable access time t ce - 90 - 150 ns address access time t aa - 90 - 150 ns output enable access time t oe - 45 - 70 ns ce low to active output t clz 0 - 0 - ns oe low to active output t olz 0 - 0 - ns ce high to high - z output t chz - 45 - 45 ns oe high to high - z output t ohz - 45 - 45 ns output hold from address change t oh 0 - 0 - ns byte/page - write cycle timing parameters parameter symbol min. typ. max. unit write cycle (erase and program) t wc - - 10 ms address setup time t as 0 - - ns address hold time t ah 50 - - ns we and ce setup time t cs 0 - - ns we and ce hold time t ch 0 - - ns oe high setup time t oes 10 - - ns oe high hold time t oeh 10 - - ns ce pulse width t cp 70 - - ns we pulse width t wp 70 - - ns we high width t wph 150 - - ns data setup time t ds 50 - - ns data hold time t dh 10 - - ns byte load cycle time t blc 0.22 - 20 0 m s byte load cycle time - out t blco 300 - - m s note: all ac timing signals observe the following guidelines for determining setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
w29ee011 - 12 - data polling and toggle bit timing parameters parameter sym. w29ee011 - 90 w29ee011 - 15 unit min. max. min. max. oe to data polling output delay t oep - 45 - 70 ns ce to data polling output delay t cep - 90 - 150 ns oe to toggle bit output delay t oet - 45 - 70 ns ce to toggle bit output delay t cet - 90 - 150 ns timing waveforms read cycle timing diagram address a16-0 dq7-0 data valid data valid high-z ce oe we t rc v ih t olz t clz t oe t ce t oh t aa t chz t ohz high-z
w29ee011 publication release date: july 1999 - 13 - revision a12 timing waveforms, continued we controlled write cycle timing diagram address a16-0 dq7-0 data valid internal write starts ce oe we t as t cs t oes t ah t blco t wc t ch t oeh t wph t wp t ds t dh ce controlled write cycle timing diagram high z data valid internal write starts ce oe we dq7-0 t as t ah t blco t wc t cph t oeh t dh t ds t cp t oes address a16-0
w29ee011 - 14 - timing waveforms, continued page write cycle timing diagram address a16-0 byte 0 byte 1 byte 2 byte n-1 byte n internal write start dq7-0 ce oe we t wc t blco t blc t wph t wp data polling timing diagram address a16-0 dq7-0 we oe ce t x x x x t cep t oeh t oep t oes wc
w29ee011 publication release date: july 1999 - 15 - revision a12 timing waveforms, continued toggle bit timing diagram address a16-0 dq6 ce oe we t oeh t oes t wc page write timing diagram software data protection mode 5555 5555 aa 55 a0 three-byte sequence for software data protection mode byte/page load cycle starts internal write starts byte n (last byte) byte 0 sw2 sw1 sw0 address a16-0 dq6 ce oe we 2aaa t wp t wph t blc t blco byte n-1 t wc
w29ee011 - 16 - timing waveforms, continued reset software data protection timing diagram sw2 sw1 sw0 address a16-0 dq7-0 ce oe we sw3 sw4 sw5 internal programming starts six-byte sequence for resetting software data protection mode t wc t wp t wph t blc t blco 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 20 5 volt - only software chip erase timing diagram sw2 sw1 sw0 address a16-0 dq7-0 ce oe we sw3 sw4 sw5 internal programming starts six-byte code for 5v-only software chip erase t wc t wp t wph t blc t blco 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10
w29ee011 publication release date: july 1999 - 17 - revision a12 ordering information part no. access time ( n s) power supply current max. ( m a) standby vdd current max. ( m a) package cycling w29ee011 - 90 90 50 100 600 mil dip 1k w29ee011 - 15 150 50 100 600 mil dip 1k w29ee011t - 90 90 50 100 type one tsop 1k w29ee011t - 15 150 50 100 type one tsop 1k w29ee011p - 90 9 0 50 100 32 - pin plcc 1k w29ee011p - 15 150 50 100 32 - pin plcc 1k w29ee01190b 90 50 100 600 mil dip 10k w29ee01115b 150 50 100 600 mil dip 10k w29ee011t90b 90 50 100 type one tsop 10k w29ee011t15b 150 50 100 type one tsop 10k w29ee011p90b 90 50 100 32 - p in plcc 10k w29ee011p15b 150 50 100 32 - pin plcc 10k notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w29ee011 - 18 - package dimensions 32 - pin p - dip 1.dimensions d max. & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dambar 5.controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 32 - pin plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.9 5 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.49 0 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.51 0 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
w29ee011 publication release date: july 1999 - 19 - revision a12 package dimensions, continued 32 - pin tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) q min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm q __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
w29ee011 - 20 - version history version date page description a9 feb. 1998 6 add pause 10 ms 7 add pause 50 ms 8 correct the time 10 ms to 10 m s 1, 17 add cycing 100 item a10 jun. 1998 1, 10, 11, 12, 17 add 70 ns bining a11 aug. 1 998 1, 2, 17, 19 add tsop package a12 jul. 1999 1, 17 change endurance cycles as 1k/10k 1, 11, 12, 17 delete 70,120 ns bining 1, 17, 18 delete sop package headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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